FPGAs for High Performance Computing

Description: The workshop introduces the fundamentals of HPC technologies and shows how FPGAs are programmed in an HPC context through the high-level synthesis (HLS) design flow, using C/C++ rather than hardware description languages. Through simple examples, participants will learn how to write synthesizable kernels, transfer data between the host and an FPGA board, and apply optimization techniques. As a case study, we will develop an accelerator for Cholesky matrix decomposition on AMD-Xilinx FPGAs.

This workshop is jointly organized by the Competence Centre for Chips (Chips.si) and the Competence Centre for High-Performance Computing (Sling.si). At the workshop, we introduce the fundamentals of HPC technologies, covering computing architectures, parallelism, and the role of hardware accelerators in modern supercomputing, and then explore how FPGAs are programmed in an HPC context through the high-level synthesis (HLS) design flow.

HLS allows application-specific accelerators to be described, debugged, and implemented on FPGAs using C/C++ rather than hardware description languages such as VHDL or Verilog. Through simple examples, participants will learn how to write synthesizable kernels, transfer data between the host and an FPGA board, and apply optimization techniques to improve speed and resource utilization.

As a case study, we will develop an accelerator for Cholesky matrix decomposition using C/C++ together with the OpenCL and XRT libraries on AMD-Xilinx FPGAs. While the sessions primarily target AMD-Xilinx boards, the principles gained apply just as well to FPGAs from other vendors.

Language: Englsih

Difficulty: Intermediate

Max. number of participants: 15

Date: 4. 11. 2026  9:00-14:00 in 5.11.2026 9:00-14:00

Virtual location:  Zoom

Target audience: Everyone is eligible to attend the workshop.

Skills gained:

•    understanding the architecture of supercomputers and heterogeneous systems
•    understanding the operation of heterogeneous computer systems with FPGA
•    understanding the FPGA technology
•    understanding the concepts of OpenCL and XRT software frameworks and HLS
•    how to write, translate, and run programs for FPGA
•    how to use HLS directives for design optimization

Workflow:  The training takes place online over two days. Participants work through remote access to a server using an SSH client and need a personal computer or laptop.

Organisers:

• Competence Centre for Chips (https://cc-chip.si/slo/) 

Predavatelji:

Več informacij lahko poiščete na spletni strani dogodka, kjer se lahko tudi prijavite.